1. Field of the Invention
The present invention relates to a MOS type field effect transistor and a manufacturing method thereof and, more particularly, to a MOS type field efect transistor having a channel area provided with thin film and a manufacturing method of such a transistor.
2. Description of the Background Art
It has been recently demanded to establish microtechnology as the density and integration tend to increase in the MOS type field effect transistor (hereinafter abbreviated as "MOSFET") in which a source for supplying a carrier and a drain for taking out the carrier are located on both sides of a capacitor consisting of a metal-oxide film-semiconductor structure provided with a metal electrode on a silicon semiconductor substrate by means of oxide film.
Incidentally, because parasitic capacity is formed inside the MOSFET owing to its structure and the time for charging and discharging of the parasitic capacity determines the operating speed of the MOSFET, it becomes possible to operate the MOSFET at high speed by minimizing the parasitic capacity.
The MOSFET is now required to have a novel structure for achieving high speed operation through miniaturization. As an example of such a novel structure, there is an SOI (Silicon On Insulator) structure in which a channel area is provided with thin film to reduce the parasitic capacity between the source and substrate as well as between the drain and substrate. FIG. 5 is a structural sectional view and a plan view illustrating a conventional n-channel MOSFET having an SOI structure.
In this drawing, the reference numeral (1) indicates a P-type silicon semiconductor substrate having the density of 1.times.10.sup.15 cm.sup.-3, and the specific resistance of 10.OMEGA..cm; numeral (2) indicates an insulator layer formed on one main surface of the foregoing P-type silicon semiconductor substrate(1); numeral (3) indicates a P-type silicon semiconductor layer having the density of 1.times.10.sup.15 cm.sup.-3 and the specific resistance of 10.OMEGA..cm formed on the main surface which does not contact the foregoing P-type silicon semiconductor substrate (1) of the foregoing insulator (2); numeral (4) indicates a channel area having the density of 1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3 ; formed by injecting boron ions into the foregoing P-type silicon semiconductor layer (3) with the acceleration voltage of 10 to 30 Kev and the dose of 1.times.10.sup.12 to 1.times.10.sup.14 cm.sup.-2 ; numeral (5) indicates an n.sup.+ type source area having the density of 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3 formed to cause the bottom thereof to contact the foregoing insulator layer (2) by injecting arsenic ions into the foregoing P-type silicon semiconductor layer (3) with the acceleration voltage of 40 Kev and the dose of 5.times.10.sup.15 cm.sup.-2 ; numeral (6), like the foregoing n.sup.+ type source area (5), indicates an n.sup.+ type drain area having the density of 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3 formed to cause the bottom thereof to contact the foregoing insulator layer (2) by injecting arsenic ions into the foregoing P-type silicon semiconductor layer (3) with the acceleration voltage of 40 Kev and the dose of 5.times.10.sup.15 cm.sup.-2 ; numeral (7) indicates a gate dielectric thin film formed on the main surface which does not contact the foregoing insulator layer (2) of the foregoing P-type silicon semiconductor layer (3); numeral (8) indicates a gate electrode formed on the foregoing gate dielectric thin film (7); numeral (9) indicates a layer insulation film formed to cover the foregoing P-type silicon semiconductor layer (3) and the foregoing gate electrode (8); numeral (10a) is a first contact hole provided on the foregoing n.sup.+ type source area; numeral (10b), like the foregoing first contact hole (10a), indicates a second contact hole provided on the foregoing n.sup.+ type drain area (6); numeral (11a) indicates a first wiring of aluminum alloy formed in the foregoing first contact hole (10a); and (11b), like the foregoing second contact hole (11a), indicates a second wiring of aluminum alloy formed in the foregoing second contact hole (10b).
Since the conventional n channel MOSFET is composed in a manner mentioned above, when a voltage over the threshold is applied to the gate electrode (8), the electron which is the carrier of the n-type semiconductor is drawn toward the surface of the channel area (4), changing the surface into the same n-type as that of the n.sup.+ type source area (5) and the n.sup.+ type drain area (6). Therefore, current flows between the n.sup.+ type source area (5) and the n.sup.+ type drain area (6). Because the density of the carrier drawn to the surface of the channel area (4) varies depending upon the voltage applied to the gate electrode (8), the amount of current flowing through the channel area (4) can be controlled by the voltage to be applied to the gate electrode (8).